library verilog;
use verilog.vl_types.all;
entity AddSign is
    generic(
        pmi_data_width  : integer := 8;
        module_type     : string  := "Add"
    );
    port(
        SA              : in     vl_logic_vector;
        SB              : in     vl_logic_vector;
        ssum            : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_data_width : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end AddSign;
